1. Field of the Invention
The present invention relates to hybrid elements of an electrically writable non-volatile memory and a DRAM and other elements such as a Logic IC, etc.
2. Description of the Related Art
Conventionally, in a non-volatile memory such as a flash memory having floating gates and control gates, a gate oxidation film below the floating gates (hereinafter referred to as a first oxidation film) is used as an oxidation film for memory cell transistors, and information is stored by causing a threshold value of a memory cell transistor to change as a result of removing or injecting electrical charge into the floating gate using CHE (channel Hot Electron) current or FN (Fowler-Nordheim) tunnel current by applying a high voltage to the first gate oxidation film.
It is required that the film thickness of the first gate oxidation film in the memory cell transistor is thin, for example 100 xc3x85, so as to carry out rewriting. However, even if a gate oxidation film as thin as, for example, 100 xc3x85 is used underneath the floating gate of the memory cell, if a capacitive coupling ratio between the control gates and the floating gates is assumed to be 0.7 then a voltage required for rewriting becomes 10V or more. If the first gate oxidation film is used directly on peripheral transistors, an electric field applied to the oxidation film becomes 10 MV/cm and it is not possible to ensure the reliability of the oxidation film.
As a result, a gate oxidation film thicker than an ordinary first gate oxidation film is applied to peripheral transistors. Specifically, a common manufacturing method forms peripheral transistors with a gate oxidation film of approximately 200 xc3x85, and with electrodes of the same material as control gates of memory cell transistors.
In the example of the related art described thus far, the case has been described where only one type of gate oxidation film is used for peripheral circuits, namely a gate oxidation film with a thickness of 200 xc3x85. However, there are also cases where transistors are formed having gate oxidation films of differing thicknesses, such as those for high withstand pressure or low voltage use. As such a manufacturing method, there is a method of respectively forming two types of gate oxidation film separately for transistors of peripheral circuits and transistors of memory cells, as disclosed in, for example, Japanese Patent Laid-open Publication No. Hei. 6-177360.
However, with the above described method, since it is necessary to respectively form two types of gate oxidation film for the memory cells and separate portions, there is a problem that the number of manufacturing steps is increased compared to a method where one only type of gate oxidation film is formed for the memory cells and other portions.
An object of the present invention is to provide a non-volatile memory in which there is no need to form two types of gate oxidation films for memory cells and separate portions, and in which gates of transistors of peripheral circuits have low resistance, and to provide a method of manufacturing the same.
The non-volatile memory of the present invention comprises memory cells having floating gates formed of first polysilicon and control gates formed of second polysilicon formed directly on top of a silicide layer, and peripheral circuits provided with transistors having gates formed of the first polysilicon formed directly on a silicide layer.
Also, the method of manufacturing the non-volatile memory having memory cells comprised of floating gates formed of first polysilicon and control gates formed of a second polysilicon comprises the steps of: forming a first oxidation film on a semiconductor substrate, forming a first polysilicon film on the first oxidation film, forming an insulating film on the first polysilicon film, forming a second polysilicon film on the insulating film, selectively removing the insulating film and the second polysilicon film at specified regions for forming transistors, forming a silicide layer on the second polysilicon film and on fixed regions of the first polysilicon film for forming transistors, and respectively patterning floating gates and control gates of transistors and memory cells.